SRAMs may be arranged in a domino-logic structure using a local bit line coupled to a number of SRAM cells and a global bit line that may be discharged when the local bit line is discharged. The bit lines in a domino SRAM are precharged high and may be discharged to ground, or “pulled down.” SRAM cells are connected in parallel to a read/write/precharge circuit through the local bit lines to form a column. The local bit lines are precharged by the read/write/precharge circuit and discharged by the selected cell during a read operation. A local bit line is coupled to a transistor which may discharge the global bit line. For multiple columns there is typically one global bit line per column. The global bit lines feed into a multiplexer, which receives a column address signal and selects the appropriate global bit line for the column selected. In order for the circuit to function, the global bit line must be precharged.
FIG. 1 is a schematic representation of a portion of a prior art SRAM circuit 100 having two columns 103A and 103B, a column A global bit line (GBL_A) 111A, and column B global bit line (GBL_B) 111B, and a multiplexer 113. SRAM cells 101 are connected to a read/write/precharge circuit 102 through a local bit line true (LBLT) 105 and a local bit line complement (LBLC) 104. LBLT 105 and LBLC 104 are precharged by a local bit line precharge line (LBL_PCH) 110 and transistors 1P1 and 1P2. A write true line (WT) 107 and its associated transistors 1N4 and 1N5, a write complement line (WC) 108 and its associated transistors 1N3 and 1N6, and a write enable line (WE) 109 and its associated transistor 1N7 control the write operations of a cell 101. GBL_A 111A and GBL_B 111B are precharged by a global bit line precharge line (GBL_PCH) 115 and transistors 1P3 and 1P4.
As an illustration, to read a “zero” from a cell 101 in column A 103A, a word line (WL) 106 turns on pass transistors 1N1 and 1N2. When the “zero” is read, LBLT 105 is pulled down while LBLC 104 remains high. The value on LBLT is inverted to a “one” by an inverter 116 and turns on a transistor 1N8, which pulls down the precharged GBL_A 111A. A column address select (CAS) 112 controls the multiplexer 113, which selects a global bit line to output to a data out line (Data_Out) 114. CAS 112 selects GBL_A 111A, and the “zero” outputs to Data_Out 114. GBL_A 111A is subsequently precharged for a next operation. This read operation requires one global bit line per column, each requiring precharging.